Nec Network Controller uPD98502 Manuel d'utilisateur télécharger pdf (Page 466)

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101

APPENDIX A MIPS III INSTRUCTION SET DETAILS

466

Preliminary User’s Manual S15543EJ1V0UM

CACHE

Cache (2/4)

CACHE

Write back from a cache goes to main memory.

The main memory address to be written is specified by the cache tag and not the physical address translated using

TLB.

TLB Refill and TLB Invalid exceptions can occur on any operation. For Index operations

Note

for addresses in the

unmapped areas, unmapped addresses may be used to avoid TLB exceptions. Index operations never cause a

TLB Modified exception. Bits 17 and 16 of the instruction code specify the cache for which the operation is to be

performed as follows.

Code Name Cache

0 I Instruction cache

1 D Data cache

2  Reserved

3  Reserved

Note Physical addresses here are used to index the cache, and they do not need to match the cache tag.

Bits 20 to 18 of this instruction specify the contents of cache operaiton. Details are provided from the next page.

1 2 ... 461 462 463 464 465 466 467 468 469 470 471 ... 594 595

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Nec Network Controller uPD98502 Manuel d'utilisateur Page 466

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