NEC PD17062 manuels

Nec PD17062 Manuel d'utilisateur (296 pages)

marque: Nec | Catégorie: Non | Taille: 1.50 MB |

Table des matières

MOS INTEGRATED CIRCUIT

ORDERING INFORMATION

FUNCTION OVERVIEW

PIN CONFIGURATION (TOP VIEW)

PD17062GC-×××-3BE

BLOCK DIAGRAM

1. PINS

RESET signal (except for P1C)

A/D Converter

High on-state

P0B3/HSCNT

P0B2/TMIN

(Hysteresis input)

2. PROGRAM MEMORY (ROM)

3. PROGRAM COUNTER (PC)

4. STACK

DD is applied

5. DATA MEMORY (RAM)

R, (r)) ← (m)

Row address

Discrimi

R and mC

8. SYSTEM REGISTER (SYSREG)

2-b0, 7BH b3), of

Comparison

Transfer

Example 1. ADD03H,11H

Specifies the source

0 b3 b2 b1 b0

9. REGISTER FILE (RF)

Peripheral hardware

StackTimerInterrupt

C bus method

(only for 2-wire method)

2) (SPb0)

9.3 CE (07H, b0)

NC pin and VSYNC pin

0 INTNC pin

1 Clock timer

2 VSYNC pin

3 Serial interface

10. DATA BUFFER (DBF)

0 to bit6.)

Peripheral

100

11. INTERRUPT

106

BANK PSW

107

NC pin)

108

NC pin) can be selected

108

Serial interface 01H

109

INTNC pin 04H

109

Timer 03H

109

VSYNC pin 02H

109

NC pin), each type of

111

NC pin) is used

114

(a) Hardware priorities

115

(b) Software priorities

115

0 of the

116

3 b2 b1 b0 b3 b2 b1 b0

121

SYNC pin

121

Active edges of interrupt

122

SYNC pinINTNC pin

122

System register restoration

131

Interrupt permission

131

12. TIMER

133

2/TMIN pin

134

2/TMIN pin by 5 or 6

134

CHECK < tSET

138

SET < error < tCHECK

140

CHECK + tTIMER < tSET

142

Interrupt pending

149

Input latch

153

DD is turned on

155

0 at address 07H)

155

14. RESET

171

Reset signal

173

(b) At clock-stop

179

During this period

182

DD is dropped

183

DD or by the CE pin, as

184

DD is turned on, they

184

Operation stopped

185

15. GENERAL-PURPOSE PORT

189

3 b2 b1 b0

191

Note Nothing is mapped to b

193

3, P0A2 pins)

194

3, P0B2, P0B1, P0B0 pins)

194

3, P1B2, P1B1, P1B0 pins)

194

3, P1C2, P1C1 pins)

194

1, P0A0 pins)

194

At reset

195

3, P0D2, P0D1, P0D0 pins)

198

3, P0C2, P0C1, P0C0 pins)

199

3, P1A2, P1A1, P1A0 pins)

199

16. SERIAL INTERFACE

201

Remark × : Don’t care

202

Remark ×: Don’t care

203

3 is used as an SO pin

205

1/SCL pin for

206

Bit position b3 b2 b1 b0

207

6789123456789

208

SCL, SCK

208

Bit counter

208

Flag name SBACK SIO0NWT

209

SIO0WRQ1 SIO0WRQ0

209

17. D/A CONVERTER

217

6 b5 b4 b3 b2 b1 b0

218

3 b2 b0b1

223

N” of the

226

(2) When fN is leading fr

227

(4) When fN is lower than fr

227

Upon reset

229

(PLLUL flag = 1)

230

19. A/D CONVERTER

233

REF = VDD ×

234

DD = 5 V

234

Flowchart

238

20. IMAGE DISPLAY CONTROLLER

240

Blank (black)

241

Background (TV screen)

241

Sample program

244

01 234 5 6789AB

249

800001 400

249

ID field Data field

250

VRAM column address

250

7 b6 b5 b4 b3 b2 b1 b0

252

0 BANK0 0800H-0BFFH

255

1 BANK1 0C00H-0F7FH

255

14 and b13 of control data)

258

10 corresponding

259

10 to b7 of the control data)

259

6 to b3 of the control data)

260

6 corresponding

260

2 to b0 of the control data)

261

7 b6 b5 b4 b3 b2 b1 b0

264

3 b2 b1 b0 b3 b2 b1 b0

264

IDC image area

265

SYNC and

267

SYNC signals supplied to the

267

SYNC signal that comes

267

20.8 SAMPLE PROGRAMS

268

269

22. INSTRUCTION SETS

277

The reserved

282

23.1 SYSTEM REGISTER

282

23.2 DATA BUFFER

282

23.3 PORT REGISTER

283

23.4 REGISTER FILES

284

NC interrupt request flag

285

23.6 OTHERS

286

64 PIN PLASTIC QFP ( 14)

290

SMD Surface Mount

291

Technology Manual

291

APPENDIX DEVELOPMENT TOOLS

292

Cautions on CMOS Devices

295

M4 94.11

296

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NEC PD17062 manuels

Nec PD17062 Manuel d'utilisateur (296 pages)

Table des matières

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